参考自http://www.eefocus.com/liuyuxue/blog/13-11/300280_d7008.html
信号赋初值以避免综合时出现锁存器。
注意警告。
FPGA 之 锁存器 (Latch)
Thank you for your reward !
- Post link: https://didongdongdi.github.io/2018/11/08/FPGA-之-锁存器-Latch/
- Copyright Notice: All articles in this blog are licensed under BY-NC-SA unless stating additionally.